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x t july 1998 american microsystems, inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 7.20.98 )6 'ljlwdo$xglr9lghr&orfn*hqhudwru,& ,62 1.0 features triple phase-locked loop (pll) device provides exact ratiometric derivation of audio, processor, and utility clocks on-chip tunable voltage-controlled crystal oscillator (vcxo) allows precise system frequency tuning serial interface for audio and utility clock frequency selection board-programmable processor clock frequency selection supports 32, 44.1, and 48khz 256x oversampled dacs as well as 384x at 44.1khz and 512x at 48khz tunable audio clock frequencies for undetectable resynchronization of audio and video streams small circuit board footprint (16-pin 0.150 2 soic) custom frequency selections available - contact your local ami sales representative for more information figure 1: block diagram vcxo serial interface sdata sclk sload fs6011 uclk processor clock pll audio clock pll utility clock pll xout xin clk_27 aclk pclk xtune psel1 psel0 2.0 description the FS6011-02 is a monolithic cmos clock generator ic designed to minimize cost and component count in digital video/audio systems. at the core of the FS6011-02 is circuitry that implements a voltage-controlled crystal oscillator when an external resonator (nominally 27mhz) is attached. the vcxo al- lows device frequencies to be precisely adjusted for use in systems that have frequency matching requirements, such as digital satellite receivers. three high-resolution phase-locked loops independently generate three other selectable frequencies derived from the vcxo frequency. these clock frequencies are re- lated to the vcxo frequency and to each other by exact ratios. the locking of all the output frequencies together can eliminate unpredictable artifacts in video systems and unpredictable electromagnetic interference (emi) performance due to frequency harmonic stacking. figure 2: pin configuration 1 16 2 3 4 5 6 7 8 15 14 13 12 11 10 9 sclk sdata sload vss xin xout xtune vdd psel1 psel0 vss pclk uclk vdd aclk clk27 fs6011 16-pin (0.150 2 ) soic
x t july 1998 2 7.20.98 )6 'ljlwdo$xglr9lghr&orfn*hqhudwru,& ,62 table 1: pin descriptions key: ai = analog input; ao = analog output; di = digital input; di u = input with internal pull-up; di d = input with internal pull-down; dio = digital input/output; di-3 = three-level digital input, do = digital output; p = power/ground; # = active low pin pin type name description 1 di sclk serial data clock 2 di sdata serial data input 3 di sload serial port load 4 p vss ground 5 ai xin vcxo feedback 6 ao xout vcxo drive 7 ai xtune vcxo tune 8 p vdd power supply (+5v) 9di d psel1 pclk select msb 10 di d psel0 pclk select lsb 11 p vss ground 12 do pclk processor clock output 13 do uclk utility clock output 14 p vdd power supply (+5v) 15 do aclk audio clock output 16 do clk27 reference clock output 3.0 functional block description 3.1 phase-locked loops each of the three on-chip plls in the fs6011 multiplies the reference frequency to the desired frequency by a ratio of integers. this frequency multiplication is exact. 3.2 output tristate control all four clock outputs of the fs6011 may be tristated to facilitate circuit board testing. to place the outputs in tristate mode, follow this sequence: 1. force xin low (i.e. ground) 2. apply power to the device 3. wait until the internal power-on reset has deasserted 4. apply a negative-going transition to the psel0 pin outputs may be re-enabled by removing and reapplying power to the fs6011. to re-enable outputs without re- moving power, apply a rising edge transition to the xin in and follow it with a falling edge transition on the psel0 pin. 3.3 digital interface digital data is placed on the sdata pin and clocked into the fs6011 internal shift register (d[0] first) with a rising edge on the sclk pin. the shift register data is trans- ferred to the fs6011 control registers with a rising edge on the sload pin. fifteen bits must be shifted into the internal registers before the parallel load can be per- formed. in addition to the normal control functions per- formed by d[13:0], there is one reserved bit, d[14], that should be set to zero. all control registers are initialized to zero on power-up. figure 3: communications protocol sclk sdata t hd:dat t lo t hi sload t su:dat t r t f t lo t hi t su:ld t hd:ld
x t july 1998 3 7.20.98 )6 'ljlwdo$xglr9lghr&orfn*hqhudwru,& ,62 3.4 voltage-controlled crystal oscillator (vcxo) the vcxo provides a tunable, low-jitter frequency refer- ence for the rest of the fs6011 system components. loading capacitance for the crystal is internal to the fs6011. no external components (other than the reso- nator itself) are required for operation of the vcxo. the resonator loading capacitance is adjustable under register control. this permits factory coarse tuning of in- expensive resonators to the necessary precision for digi- tal video applications. refer to section 4.6. continuous fine-tuning of the vcxo frequency is accom- plished by varying the voltage on the xtune pin. the total change (from one extreme to the other) in effective loading capacitance is 1.5pf nominal. the oscillator operates the crystal resonator in the paral- lel-resonant mode. crystal warping, or the pulling of the crystal oscillation frequency, is accomplished by altering the effective load capacitance presented to the crystal by the oscillator circuit. the actual amount that changing the load capacitance alters the oscillator frequency will be dependent on the characteristics of the crystal as well as the oscillator circuit itself. specifically, the motional capacitance of the crystal (usu- ally referred to by crystal manufacturers as c 1 ), the static capacitance of the crystal (c 0 ), and the load capacitance (c l ) of the oscillator determine the warping capability of the crystal in the oscillator circuit. a simple formula to obtain the warping capability of a crystal oscillator is: () ()() c c c c c c c ppm f l l l l 1 0 2 0 6 1 2 1 2 10 ) ( + + - = d where c l1 and c l2 are the two extremes of the applied load capacitance. a crystal with the following parameters is used. with c 1 = 0.02pf, c 0 = 5pf, c l1 = 10pf, and c l2 = 22.66pf, the coarse tuning range is () ()() ppm . . . f 305 10 5 66 22 5 2 10 6 10 66 22 02 0 = + + - = d . 4.0 programming information table 2: register summary bit d[x] register bit description 0 aclk select (lsb) 1 aclk select 2 aclk select (msb) aclk off-speed mode bit = 0 disable off-speed mode 3 bit = 1 enable off-speed mode aclk speed control bit = 0 low speed 4 bit = 1 high speed 5 uclk select (lsb) 6 uclk select 7 uclk select (msb) clk27 select bit = 0 selects vcxo frequency 8 bit = 1 selects uclk frequency 9 crystal oscillator coarse tune (lsb) 10 crystal oscillator coarse tune 11 crystal oscillator coarse tune 12 crystal oscillator coarse tune (msb) vcxo enable/disable control bit = 0 disable vcxo mode 13 bit = 1 enable vcxo mode 14 reserved (should be set to 0)
x t july 1998 4 7.20.98 )6 'ljlwdo$xglr9lghr&orfn*hqhudwru,& ,62 4.1 audio pll clock frequencies (aclk) the aclk frequency is controlled by register bits d[0], d[1], and d[2] accessed via the serial interface. the aclk frequencies listed below are derived via the pll divider ratio from a reference frequency of 27mhz. table 3: aclk frequency select d[2] d[1] d[0] pll divider ratio audio oversampling aclk (mhz) 0 0 0 1024 / 2250 48khz x 256 12.288 0 0 1 1024 / 3375 32khz x 256 8.192 0 1 0 1024 / 4500 48khz x 256 / 2 6.144 0 1 1 1024 / 6750 32khz x 256 / 2 4.096 1 0 0 1568 / 3750 44.1khz x 256 11.2896 1 0 1 1568 / 2500 44.1khz x 384 16.9344 1 1 0 1568 / 7500 44.1khz x 256 / 2 5.6448 1 1 1 1024 / 1125 48khz x 512 24.576 note: contact ami for custom pll frequencies 4.2 audio clock off-speed frequencies the aclk frequencies shown may be smoothly modified to a slightly higher or lower value under register control. register bit d[3] must be a logic-one to activate this mode. the value of d[4] controls whether the frequency will be adjusted slightly low (d[4] = 0) or high (d[4] = 1). table 4: audio off speed frequencies d[4] d[3] d[2] d[1] d[0] pll divider ratio aclk (mhz) 01000 1023 / 2250 12.276 01001 1023 / 3375 8.184 01010 1023 / 4500 6.138 01011 1023 / 6750 4.092 01100 1567 / 3750 11.2824 01101 1567 / 2500 16.9236 01110 1567 / 7500 5.6412 01111 1023 / 1125 24.5520 11000 1025 / 2250 12.3000 11001 1025 / 3375 8.2000 11010 1025 / 4500 6.1500 11011 1025 / 6750 4.1000 11100 1569 / 3750 11.2968 11101 1569 / 2500 16.9432 11110 1569 / 7500 5.6484 11111 1025 / 1125 24.6000 4.3 utility pll clock frequencies (uclk) the uclk frequency is controlled by register bits d[5], d[6] and d[7], accessed via the serial interface. uclk frequencies listed below are derived via the pll divider ratio from a reference frequency of 27mhz. table 5: uclk frequency select d[7] d[6] d[5] pll divider ratio uclk (mhz) 0 0 0 16 / 27 16.0000 0 0 1 35 / 33 28.6363 0 1 0 1568 / 3750 11.2896 0 1 1 1 27.0000 1 0 0 544 / 375 39.1680 1 0 1 728 / 375 52.4160 1 1 0 10 / 9 30.0000 1 1 1 1024 / 1125 24.5760 note: contact ami for custom pll frequencies 4.4 processor pll frequencies (pclk) the pclk frequency is controlled by the logic levels on the psel0 and psel1 inputs. these inputs have weak pull-downs. pclk frequencies listed below are derived via the pll divider ratio from a reference frequency of 27mhz. table 6: pclk frequency select psel1 psel0 pll divider ratio pclk (mhz) 0 0 32 / 27 32.0000 0 1 40 / 27 40.0000 1 0 50 / 27 50.0000 1 1 60 / 41 39.5122 note: contact ami for custom pll frequencies
x t july 1998 5 7.20.98 )6 'ljlwdo$xglr9lghr&orfn*hqhudwru,& ,62 4.5 reference frequencies (clk27) the clk27 output frequency is controlled by register bit d[8] that selects either the vcxo reference frequency or the uclk frequency. table 7: clk27 frequency select d[8] clk27 output 0 vcxo frequency 1 uclk frequency 4.6 vcxo coarse tuning and enable the vcxo may be coarse tuned by a programmable ad- justment of the crystal load capacitance via d[12:9]. the actual amount of frequency warping caused by the tuning capacitance will depend on the crystal used. the vcxo tuning capacitance includes an external 6pf load ca- pacitance (12pf from the xin pin to ground and 12pf from the xout pin to ground). the fine tuning capability of the vcxo can be enabled by setting d[13] to a logic-one or disabled by clearing the bit to a logic-zero. table 8: vcxo tuning capacitance d[12] d[11] d[10] d[9] vcxo tuning capacitance (pf) 0 0 0 0 10.00 0 0 0 1 10.84 0 0 1 0 11.69 0 0 1 1 12.53 0 1 0 0 13.38 0 1 0 1 14.22 0 1 1 0 15.06 0 1 1 1 15.91 1 0 0 0 16.75 1 0 0 1 17.59 1 0 1 0 18.43 1 0 1 1 19.28 1 1 0 0 20.13 1 1 0 1 20.97 1 1 1 0 21.81 1 1 1 1 22.66 figure 4 shows the typical effect of the coarse and fine tuning mechanisms. the difference in vcxo frequency in parts-per-million (ppm) is shown as the fine tuning volt- age on the xtune pin varies from 0v to 5v. the coarse tune range as shown is about 350ppm. as the crystal load capacitance is increased (with increasing coarse tune setting) the frequency is pulled somewhat less with each coarse step and the fine tuning range decreases. the fine tuning range always overlaps a few coarse tun- ing ranges, eliminating the possibility of holes in the vcxo response. note that different crystal warping char- acteristics will change the scaling on the y-axis, but not the overall characteristic of the curves. figure 4: vcxo coarse and fine tuning vcxo range (ppm) vs. xtune voltage (v) -200 -150 -100 -50 0 50 100 150 200 0123456789101112131415 coarse tune setting d[11:14] vcxo range (ppm) xtune voltage = 0.0v xtune voltage = 5.0v
x t july 1998 6 7.20.98 )6 'ljlwdo$xglr9lghr&orfn*hqhudwru,& ,62 5.0 electrical specifications table 9: absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. exposure to maximum rati ng conditions for extended conditions may affect device performance, functionality, and reliability. parameter symbol min. max. units supply voltage (v ss = ground) v dd v ss -0.5 7 v input voltage, dc v i v ss -0.5 v dd +0.5 v output voltage, dc v o v ss -0.5 v dd +0.5 v input clamp current, dc (v i < 0 or v i > v dd )i ik -50 50 ma output clamp current, dc (v i < 0 or v i > v dd )i ok -50 50 ma storage temperature range (non-condensing) t s -65 150 c ambient temperature range, under bias t a -55 125 c junction temperature t j 125 c lead temperature (soldering, 10s) 260 c input static discharge voltage protection (human-body model) 2 kv caution: electrostatic sensitive device permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy ele c- trostatic discharge. table 10: operating conditions parameter symbol conditions/description min. typ. max. units supply voltage v dd 5v 10% 4.5 5 5.5 v ambient operating temperature range t a 070c output load capacitance c l 15 pf crystal resonator frequency f xin 24 27 28 mhz crystal resonator motional capacitance c mot at cut 25 ff serial data transfer rate 10 100 kb/s
x t july 1998 7 7.20.98 )6 'ljlwdo$xglr9lghr&orfn*hqhudwru,& ,62 table 11: dc electrical specifications unless otherwise stated, v dd = 5.0v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. where given, min and max characterization data are 3 s from typical. negative currents indicate current flows out of the device. parameter symbol conditions/description min. typ. max. units overall supply current, dynamic, with loaded outputs i dd f clk = 27mhz; c l ? 50pf 58 80 ma serial communication inputs (sclk, sdata, sload) high-level input voltage v ih 2.4 v dd +0.3 v low-level input voltage v il v ss -0.3 0.8 v hysteresis voltage v hys 300 mv input leakage current i i -1 1 m a pclk select inputs (psel0, psel1) high-level input voltage v ih 2.4 v dd +0.3 v low-level input voltage v il v ss -0.3 0.8 v high-level input current (pull-down) i ih v ih = 5v 5 12.7 50 m a low-level input current i il -1 1 m a crystal oscillator feedback (xin) threshold bias voltage * v th 0.5v dd v input leakage current i i -1 1 m a crystal loading capacitance * c l(xtal) as seen by an external crystal connected to xin and xout; vcxo tuning disabled 10 pf input loading capacitance * c l(xin) as seen by an external clock driver on xin; xout unconnected; vcxo disabled 20 pf crystal oscillator drive (xout) v o = 0v; d[13] = 0 -45 high-level output source current * i oh v o = 0v, v(xtune) = 5v; d[13] = 1 -52 ma v o = 5v; d[13] = 0 53 low-level output sink current * i ol v o = 5v, v(xtune) = 5v; d[13] = 1 63 ma vcxo tuning input (xtune) input leakage current i i -1 1 m a clock outputs (aclk, clk27, pclk, uclk) high-level output source current * i oh v o = 2.4v -46 ma low-level output sink current * i ol v o = 0.4v 64 ma z oh v o = 0.5v dd ; output driving high 53 output impedance * z ol v o = 0.5v dd ; output driving low 57 w tristate output current i oz -10 +10 m a short circuit source current * i osh v o = 0v; shorted for 30s, max. -60 ma short circuit sink current * i osl v o = 5v; shorted for 30s, max. 65 ma
x t july 1998 8 7.20.98 )6 'ljlwdo$xglr9lghr&orfn*hqhudwru,& ,62 table 12: ac timing specifications unless otherwise stated, v dd = 5.0v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. where given, min and max characterization data are 3 s from typical. parameter symbol conditions/description clock (mhz) min. typ. max. units clock output (aclk) 12.288 48 52 8.192 48 52 6.144 48 52 4.096 48 52 11.289 47 52 16.344 48 52 5.644 48 52 duty cycle * from rising edge to rising edge at 2.5v 24.576 47 51 % 12.288 740 8.192 760 6.144 730 4.096 710 11.289 650 16.344 570 5.644 680 jitter, absolute (long term) * t j(ab) measured from rising edge to 1 st rising edge after 0.1s at 2.5v; c l = 15pf, f ref = 27mhz 24.576 730 ps 12.288 370 8.192 270 6.144 190 4.096 140 11.289 470 16.344 680 5.644 240 jitter, period * t j( d p) measured on the rising edges at 2.5v; c l = 15pf, f ref = 27mhz 24.576 770 ps rise time * t r v o = 0.5v to 4.5v; c l = 15pf 3.5 ns fall time * t f v o = 4.5v to 0.5v; c l = 15pf 2.3 ns clock stabilization time * t stb output active from power-up 740 m s
x t july 1998 9 7.20.98 )6 'ljlwdo$xglr9lghr&orfn*hqhudwru,& ,62 table 13: ac timing specifications, continued unless otherwise stated, v dd = 5.0v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. where given, min and max characterization data are 3 s from typical. parameter symbol conditions/description clock (mhz) min. typ. max. units clock output (uclk) 16.000 48 52 28.636 48 52 11.289 48 52 27.000 44 48 39.168 43 47 52.416 42 46 30.000 48 52 duty cycle * from rising edge to rising edge at 2.5v 24.576 48 52 % 16.000 580 28.636 620 11.289 780 27.000 2800 39.168 640 52.416 780 30.000 650 jitter, absolute (long term) * t j(ab) measured from rising edge to 1 st rising edge after 0.1s at 2.5v; c l = 15pf, f ref = 27mhz 24.576 680 ps 16.000 250 28.636 400 11.289 400 27.000 900 39.168 670 52.416 1500 30.000 790 jitter, period * t j( d p) measured on the rising edges at 2.5v; c l = 15pf, f ref = 27mhz 24.576 680 ps rise time * t r v o = 0.5v to 4.5v; c l = 15pf 3.6 ns fall time * t f v o = 4.5v to 0.5v; c l = 15pf 2.4 ns clock stabilization time * t stb output active from power-up 380 m s
x t july 1998 10 7.20.98 )6 'ljlwdo$xglr9lghr&orfn*hqhudwru,& ,62 table 14: ac timing specifications, continued unless otherwise stated, v dd = 5.0v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. where given, min and max characterization data are 3 s from typical. parameter symbol conditions/description clock (mhz) min. typ. max. units clock output (pclk) 32.000 48 52 40.000 48 52 50.000 48 52 duty cycle * from rising edge to rising edge at 2.5v 39.512 48 52 % 32.000 410 40.000 620 50.000 630 jitter, absolute (long term) * t j(ab) measured from rising edge to 1 st rising edge after 0.1s at 2.5v; c l = 15pf, f ref = 27mhz 39.512 620 ps 32.000 430 40.000 460 50.000 530 jitter, period * t j( d p) measured on the rising edges at 2.5v; c l = 15pf, f ref = 27mhz 39.512 670 ps rise time * t r v o = 0.5v to 4.5v; c l = 15pf 3.6 ns fall time * t f v o = 4.5v to 0.5v; c l = 15pf 2.4 ns clock stabilization * t stb output active from power-up 400 m s clock output (clk27) duty cycle * crystal oscillator frequency out, from rising edge to rising edge at 2.5v 27 44 48 % clock stabilization time * t stb output active from power-up 150 m s rise time * t r v o = 0.5v to 4.5v; c l = 15pf 3.8 ns fall time * t f v o = 4.5v to 0.5v; c l = 15pf 2.9 ns table 15: serial interface timing specifications unless otherwise stated, v dd = 5.0v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. where given, min and max characterization data are 3 s from typical. parameter symbol conditions/description min. max. units sclk clock frequency f sclk 0 100 khz set up time, load t su:ld sload 4.7 m s hold time, load t hd:ld sload 4.0 m s set up time, data t su:dat sdata 250 ns hold time, data t hd:dat sdata 0 m s rise time t r sdata, sclk 1000 ns fall time t f sdata, sclk 300 ns high time, serial clock t h sclk 4.0 m s low time, serial clock t l sclk 4.7 m s
x t july 1998 11 7.20.98 )6 'ljlwdo$xglr9lghr&orfn*hqhudwru,& ,62 6.0 package information table 16: 16-pin soic (0.150") package dimensions dimensions inches millimeters min. max. min. max. a 0.061 0.068 1.55 1.73 a1 0.004 0.0098 0.102 0.249 a2 0.055 0.061 1.40 1.55 b 0.013 0.019 0.33 0.49 c 0.0075 0.0098 0.191 0.249 d 0.386 0.393 9.80 9.98 e 0.150 0.157 3.81 3.99 e 0.050 bsc 1.27 bsc h 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 l 0.016 0.035 0.41 0.89 q 0 8 0 8 be d a 1 seating plane h e 16 1 all radii: 0.005" to 0.01" base plane a 2 c l q 7 typ. h x 45 a x t r table 17: 16-pin soic (0.150") package characteristics parameter symbol conditions/description typ. units thermal impedance, junction to free-air q ja air flow = 0 m/s 108 c/w corner lead 4.0 lead inductance, self l 11 center lead 3.0 nh lead inductance, mutual l 12 any lead to any adjacent lead 0.4 nh lead capacitance, bulk c 11 any lead to v ss 0.5 pf
x t july 1998 12 7.20.98 )6 'ljlwdo$xglr9lghr&orfn*hqhudwru,& ,62 7.0 ordering information ordering code device number font package type operating temperature range shipping configuration 11228-003 fs6011 -02 16-pin (0.150) soic (small outline package) 0 c to 70 c (commercial) tube 11228-005 fs6011 -02 16-pin (0.150) soic (small outline package) 0 c to 70 c (commercial) tape-and-reel copyright ? 1998 american microsystems, inc. devices sold by ami are covered by the warranty and patent indemnification provisions appearing in its terms of sale only. ami makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the fr eedom of the described devices from patent infringement. ami makes no warranty of merchantability or fitness for any purposes. ami re - serves the right to discontinue production and change specifications and prices at any time and without notice. amis products are intended for use in commercial applications. applications requiring extended temperature range, unusual environmental require- ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recom- mended without additional processing by ami for such applications. american microsystems, inc., 2300 buckskin rd., pocatello, id 83201, (208) 233-4690, fax (208) 234-6796, www address: http://www.amis.com e-mail: tgp@amis.com
x t july 1998 13 7.20.98 )6 'ljlwdo$xglr9lghr&orfn*hqhudwru,& ,62 8.0 demonstration board a simple demonstration board and dos-based software is available from american microsystems that illustrates the capabilities of the fs6011. the board schematic is shown below. components listed with an asterisk (*) are not re- quired in an actual application, and are used here to preserve signal integrity with the cabling associated with the board. a cabled interface between a computer parallel port (db25 connector) and the board (j1) is provided. contact your local sales representative or the company directly for more information. figure 5: board schematic fs6011 sclk sdata sload vss xin xout xtune vdd clk27 aclk vdd uclk pclk vss psel0 psel1 rp1 1k c1 2.2f c3 0.1f r3* 100 r2* 100 r1* 100 r5* 100 r4* 100 r6 10 r7 10 c2 2.2f c4 0.1f y1 27mhz aclk clk27 uclk pclk psel1 psel0 sclk sdata sload c5* 100pf +5v 5 4 1 2 3 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 jp2 jp1 j1* 6 +5v +5v gnd r8* 47 r9* 47 r10* 47 r11* 47 +5v +5v c7 12pf c6 12pf
x t july 1998 14 7.20.98 )6 'ljlwdo$xglr9lghr&orfn*hqhudwru,& ,62 8.1 contents demonstration board interface cable (db25 to 6-pin connector) data sheet demonstration software, including: - install.bat 0.75kb - fs6011.bat 0.24kb - fs6011g.bas 5.3kb 8.2 requirements pc running ms-dos or ms windows 3.1x, with ac- cessible parallel (lpt1) port ms-qbasic v. 1.1 or later (or equivalent software) 6.3kb available space on drive c: 8.3 board setup and software installa- tion instructions 1. at the appropriate disk drive prompt (a:\) type install to automatically copy demo files to the c: drive. note: this demo software requires microsoft qba- sic or equivalent to run. make sure the directory containing qbasic.exe is in the dos path statement, or move the demo files to a directory containing ba- sic. 2. connect a +5 volt power supply to the board: red = +5v, black = ground. 3. remove all software keys from the computer parallel port. 4. connect the supplied interface cable to the parallel port (db25 connector) and to the demo board (6-pin connector). make sure the cable is facing away from the board C pin 1 is the red wire. 5. connect the clock outputs to the target application board with a twisted-pair cable. 8.4 demo program 1. type fs6011 at the c:\fs6011 prompt to run the qbasic-based demo program. 2. the following banner should appear: **************************************** * * * fs6011 utility program * * * * press any key to continue..... * * * **************************************** 3. after pressing any key, a menu should appear con- taining a list of the program hot keys, a message that the computer parallel (lpt1) port was found, and the address at which the port was found. *********************** * fs6011 pgm. utility * * * * chip (r)efresh * * chip (i)nitialize * * (a)clk = 0 * * a(o)ffset = 0 * * (c)lk27 = 0 * * (u)clk = 0 * * (v)cxo = 0 * * vcxo (e)nable = 0 * * (p)clk = 0 * * e(x)it * *********************** refer to table 18 for a description of each hot key. 4. to change the frequency of the desired clock, press the appropriate hot key. the keys are not case sensi- tive. 5. refer (in the fs6011 data sheet) to table 3 and table 4 for aclk frequencies, table 5 for uclk fre- quencies, and table 6 for pclk frequencies. 6. observe the response to the hot key selection. re- peated pressing of the same key will scroll through the entire range of frequencies for the selected clock, returning to the initial frequency. 7. pressing a hot key strobes a 15-bit message to the demo board via the interface cable. the response to the key selection is shown below: writing... (0x000) binary: lsb 000000000000000 msb where the numbers are the data in hex and binary. note that the pclk frequency is changed by directly ad- dressing pins 4 and 5 (psel0 and psel1) of the device. therefore the hot key response message will be un- changed when selecting the ( p )clk hot key. press x to exit the demo program.
x t july 1998 15 7.20.98 )6 'ljlwdo$xglr9lghr&orfn*hqhudwru,& ,62 table 18: hot key description command hot key bits range description refresh r reloads the register bit values into the device initialize i initializes all register bit values to zero (default setting) aclk a 0-2 000-111 cycles through aclk frequencies (table 3) aclk offset o 3-4 00-11 bit 3 enables or disables off- speed mode; bit 4 adjusts aclk off-speed high or low uclk u 5-7 000-111 cycles through uclk frequencies (table 5) clk27 c 8 0-1 switches the clk27 output between the vcxo and uclk frequency vcxo v 9-12 0000- 1111 digital coarse tune adjustment of the vcxo vcxo enable e13 0-1 enables fine tune of the vcxo via the xtune pin pclk p - 00-11 cycles through pclk frequencies via psel0 and psel1 pins (table 6) exit x exits the demo program table 19: cable interface color j1 db25 signal red 1 2 sclk white 2 16 sdata green 3 8 sload blue 4 5 psel1 brown 5 4 psel0 black 6 25 gnd figure 6: board silkscreen figure 7: board traces - component side left right figure 8: board traces - solder side right left

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